Cooling Channel Design Optimization for High Power Multi-chip Packages

Thermal management is a major challenge in next-generation high-performance computing systems, particularly for heterogeneous multi-chip packages such as the NVIDIA GB200 Grace Blackwell Superchip. This work develops a physics-based computational framework to optimize embedded cooling channel layouts for high-power multi-chip modules, coupling steady-state heat conduction with a porous-media representation of coolant transport and a row-wise coolant energy balance. An interdigitated cooling architecture is parameterized by channel count, width, and expansion over chip regions, and a surrogate-based mixed-integer quadratic programming formulation minimizes peak and average chip temperatures with constraints that increase cooling near GPU regions. Applied to a representative two-GPU, one-CPU configuration, the optimal design reduces peak temperature by 140.45 °C and average temperature by 35.87 °C versus baseline, with maximum and average temperatures remaining below the 95 °C operating limit.